After a painful few days programming, trying to identify why I couldn’t do a simple thing like load SRAM with data, I found that I’d mis-typed one of the port names in the init routine. After editing the single character that was incorrect, it sprang into action!

I quickly modified the program to load a ‘proper’ Z80 routine and tried it out. It was a simple program, loading 50 bytes of RAM positioned just about the main code with a value. I first ran the AVR code to load the Z80, then manually switched off the /BUSRQ line (a modification I had to hardwire to the board) and reset the Z80. I then ran a read program on the AVR and the value I’d chosen was there in the SRAM! I changed the value a couple of times and re-ran the test to verify it was working.

;Z80 Test Program

DESTINATION_SIZE equ 50
.org 0000h
start:
LD HL, Storea                                    ; point to the source
LD DE, Storea + 1                              ; point to the destination
LD BC, DESTINATION_SIZE – 1      ; copying this many bytes
LD (HL), 170                                      ; put a value in the 1st pos
LDIR                                                  ; move 1 to 2, 2 to 3…
Finish:
NOP
NOP
NOP
NOP
JP Finish                                              ;Infinite Loop
Storea:
DEFS 50

end

The next step is to re-write the loading program entirely, in a more tidy manner, and test the Z80 properly when the two missing chips for the output port are delivered.

I’d like to say a big thank you to Bill Rowe who gave me some great advice and suggested ideas as I went along. I’m sure I will find his help invaluable in the future as I develop the ZAViouR Board.

For those who would like to follow the progress as it happens, I have a Hackaday.io page devoted to the project. You can find it at: Hacakday.io

 Here’s a quick video of me resetting the board twice. You can see the /M1 light flicker (once I get my hand out of the way!) and then go off and on as the Z80 resets.

In the video you can also see the hard-wired /BUSRQ switch which will be re-routed to the AVR in the next version of the board. The next version of the board will have improvements based on experiences with the current version. It will have 64Kb of SRAM and the address lines will be driven from the AVR via a port expander. This will free up plenty of AVR GPIOs for other tasks.